not_IO@lemmy.blahaj.zone to Programmer Humor@programming.devEnglish · 14 days agomegaboollemmy.blahaj.zoneimagemessage-square28fedilinkarrow-up1232arrow-down11file-text
arrow-up1231arrow-down1imagemegaboollemmy.blahaj.zonenot_IO@lemmy.blahaj.zone to Programmer Humor@programming.devEnglish · 14 days agomessage-square28fedilinkfile-text
minus-squareYorick@piefed.sociallinkfedilinkEnglisharrow-up14·13 days agoMay I introduce the VHDL STD library where you can set an output to “don’t care”: Wikipedia IEEE-1164 As an embedded electronics engineer discovering VHDL was a blast and a mindfuck!
minus-squarewhite_nrdy@programming.devlinkfedilinkarrow-up5·13 days agoDon’t worry, VHDL is still a mindfuck sometimes even after being an FPGA engineer for years (mostly only using VHDL). It’s such a cool language, and I am glad you discovered and are enjoying it!
May I introduce the VHDL STD library where you can set an output to “don’t care”:
Wikipedia IEEE-1164
As an embedded electronics engineer discovering VHDL was a blast and a mindfuck!
Don’t worry, VHDL is still a mindfuck sometimes even after being an FPGA engineer for years (mostly only using VHDL). It’s such a cool language, and I am glad you discovered and are enjoying it!